336 lines
12 KiB
C++
336 lines
12 KiB
C++
/**
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* \file
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* \brief Implementation of the Driver for the AD5791
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* Digital to Analog Converter Board
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*
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*
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* The board inverts all digital inputs.
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*/
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#include "AD5791.h"
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#include "../../core/states.h"
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#include <cstdio>
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#include <cmath>
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#include <iostream>
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#include <list>
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#include <vector>
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#include <algorithm>
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using std::reverse;
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using std::cout;
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using std::vector;
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#ifndef TIMING
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#define TIMING 9e-8
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#endif
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// The bit depth of the DAC
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#define DAC_DATA_BITS 20
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#define DAC_CONTROL_BITS 4
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// The channel configuration
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#define DATA_BIT 18//18
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#define CLK_BIT 16//16
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// this bit needs to be set to write the DAC register
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#define WRITE_DAC 1<<20
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// software control register
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#define RESET 1
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#define CLR 2
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#define LDAC 4
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// control register
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// Linearity error compensation for varying reference input spans.
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#define LINCOMP_10V 0*1<<9 + 0*1<<8 + 0*1<<7 + 0*1<<6
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#define LINCOMP_12V 1*1<<9 + 0*1<<8 + 0*1<<7 + 1*1<<6
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#define LINCOMP_16V 1*1<<9 + 0*1<<8 + 1*1<<7 + 0*1<<6
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#define LINCOMP_19V 1*1<<9 + 0*1<<8 + 1*1<<7 + 1*1<<6
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#define LINCOMP_20V 1*1<<9 + 1*1<<8 + 0*1<<7 + 0*1<<6
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// SDO pin enable/disable control.
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#define SDODIS 32
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// DAC register coding select.
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#define DAC_CODING_SELECT 16
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// DAC tristate control.
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#define DACTRI 8
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// Output ground clamp control. (set by default)
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#define OPGND 4
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// Output amplifier configuration control. (set by default)
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#define RBUF 2
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AD5791::AD5791(int myid) : id(myid) {
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dac_value = 0;
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set_latch_bit(17);
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}
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AD5791::~AD5791() {}
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// This sets the dac_value
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void AD5791::set_dac(signed dw) {
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dac_value = dw;
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}
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void AD5791::set_latch_bit(int le_bit)
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{
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latch_bit = le_bit;
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}
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// This sets the DAC
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void AD5791::set_dac(state &experiment) {
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state_sequent *exp_sequence = dynamic_cast<state_sequent *>(&experiment);
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if (exp_sequence == NULL)
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// is a very state on top level, todo: change interface
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throw pfg_exception("cannot work on a single state, sorry (todo: change interface)");
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else {
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for (state_sequent::iterator child_state = exp_sequence->begin();
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child_state != exp_sequence->end(); ++child_state) {
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set_dac_recursive(*exp_sequence, child_state);
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}
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std::cout << "first state"<< std::endl;
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// Set DAC to 0 at start of experiment
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set_dac_to_zero(exp_sequence, exp_sequence->begin());
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// but first initialize DAC
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init_dac(exp_sequence, exp_sequence->begin());
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// And at the end of the experiment set DAC to zero
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set_dac_to_zero(exp_sequence, exp_sequence->end());
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}
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}
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state_sequent* AD5791::tx_bit(unsigned int bit) {
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state_sequent* tx = new state_sequent();
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ttlout* ttl_state = new ttlout();
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state s(TIMING);
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s.push_back(ttl_state);
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ttl_state->ttls = bit*(1<<DATA_BIT) + (1 << CLK_BIT);
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tx->push_back(s.copy_new());
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ttl_state->ttls = (1<<DATA_BIT);
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tx->push_back(s.copy_new());
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return tx;
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}
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void AD5791::set_dac_to_zero(state_sequent* exp_sequence, state::iterator where) {
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// 0001 0000 0000 0000 0000 0000
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state s(TIMING);
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ttlout* ttl_state = new ttlout();
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ttl_state->id = 0;
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s.push_front(ttl_state);
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// test exp_sequence->insert(where, tx_bit(1));
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exp_sequence->insert(where, tx_bit(1));
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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// 1
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ttl_state->ttls = (1<<DATA_BIT) + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = (1<<DATA_BIT);
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exp_sequence->insert(where, s.copy_new());
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// the rest
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state_sequent *rep_sequence = new state_sequent();
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rep_sequence->repeat = DAC_DATA_BITS;
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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rep_sequence->push_back(s.copy_new());
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ttl_state->ttls = 0;
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rep_sequence->push_back(s.copy_new());
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exp_sequence->insert(where, rep_sequence);
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//read in the word
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = (1 << latch_bit);
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exp_sequence->insert(where, s.copy_new());
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}
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void AD5791::init_dac(state_sequent *exp_sequence, state::iterator where) {
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state s(TIMING);
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ttlout *ttl_state = new ttlout();
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ttl_state->id = 0;
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s.push_front(ttl_state);
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// 0010 0000 0000 0000 0000 0000
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where,s.copy_new());
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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// 1
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ttl_state->ttls = (1<<DATA_BIT) + (1 << CLK_BIT);
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exp_sequence->insert(where,s.copy_new());
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ttl_state->ttls = (1<<DATA_BIT);
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exp_sequence->insert(where,s.copy_new());
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// 0
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = 0;
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exp_sequence->insert(where,s.copy_new());
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// the rest
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state_sequent *rep_sequence = new state_sequent();
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rep_sequence->repeat = DAC_DATA_BITS;
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ttl_state->ttls = 0 + (1 << CLK_BIT);
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rep_sequence->push_back(s.copy_new());
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ttl_state->ttls = 0;
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rep_sequence->push_back(s.copy_new());
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exp_sequence->insert(where, rep_sequence);
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//read in the word
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ttl_state->ttls = 0;
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exp_sequence->insert(where, s.copy_new());
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ttl_state->ttls = (1 << latch_bit) + (1<<CLK_BIT);
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s.length = 180e-9;
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exp_sequence->insert(where, s.copy_new());
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}
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// This loops recursive through the state tree
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void AD5791::set_dac_recursive(state_sequent &the_sequence, state::iterator &the_state) {
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state_sequent *a_sequence = dynamic_cast<state_sequent *>(*the_state);
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// Am I a sequence? Yes? Go one sequence further
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if (a_sequence != NULL) {
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for (state_sequent::iterator child_state = a_sequence->begin(); child_state != a_sequence->end(); ++child_state)
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set_dac_recursive(*a_sequence, child_state);
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}
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// I am not a sequence, but a state
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else {
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state *this_state = dynamic_cast<state *>(*the_state);
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if (this_state == NULL)
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throw pfg_exception("state_atom in state_sequent not expected");
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analogout *dac_analog_out = NULL;
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// find an analogout section with suitable id
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state::iterator pos = this_state->begin();
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while (pos != this_state->end()) { // state members loop
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analogout *aout = dynamic_cast<analogout *>(*pos); // initialize new analogout from state
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if (aout != NULL)
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std::cout << aout->id << std::endl;
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// This is for me, analogout is != NULL (there is an analogout) and has my ID
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if (aout != NULL && aout->id == id) {
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if (dac_analog_out == NULL) {
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// save the information of this aout
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dac_analog_out = aout;
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}
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// there is no place for me here
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else {
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throw pfg_exception("found another DAC section, ignoring");
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delete aout;
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}
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// remove the analog out section
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this_state->erase(pos++);
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} else {
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std::cout << "nope" << std::endl;
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++pos;
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}
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} // state members loop
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if (dac_analog_out != NULL) { // state modifications
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//std::cout<<"found a analog out section, value="<<dac_analog_out->dac_value<<std::endl;
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// check the length of the state
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if (this_state->length < TIMING * (DAC_CONTROL_BITS + DAC_DATA_BITS) * 2 + 1)
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throw pfg_exception("AD5791: time is too short to save DAC information");
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else {
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// copy of original state
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state *register_state = new state(*this_state);
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ttlout *register_ttls = new ttlout();
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register_ttls->id = 0;
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register_state->length = TIMING;
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register_state->push_back(register_ttls);
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if (dac_analog_out->dac_value > (pow(2.0, int(DAC_DATA_BITS - 1)) - 1))
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throw pfg_exception("dac_value too high");
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if (abs(dac_analog_out->dac_value) > pow(2.0, int(DAC_DATA_BITS - 1)))
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throw pfg_exception("dac_value too low");
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// set dac write register 1<<20
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dac_analog_out->dac_value += WRITE_DAC;
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vector<int> dac_word;
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// generate the bit pattern, this is MSB last
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for (int j = 0; j < (DAC_DATA_BITS + DAC_CONTROL_BITS); j++) {
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int bit = dac_analog_out->dac_value & 1;
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dac_word.push_back(bit);
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dac_analog_out->dac_value >>= 1;
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std::cout << bit;
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}
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// reverse the bit pattern (MSB first)
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reverse(dac_word.begin(), dac_word.end());
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// need one clock cycle to read in bit
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// latch enable (LE) should always be high while doing so
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// except for the last bit
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// do run length encoding, grouping same bit values in loops
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int last_seen_bit = dac_word[0];
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int last_seen_bit_count = 1;
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for (int i = 1; i < (DAC_DATA_BITS + DAC_CONTROL_BITS) + 1; i++) {
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if (i == (DAC_DATA_BITS + DAC_CONTROL_BITS) || last_seen_bit != dac_word[i]) {
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// so we have to write the bits
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// either because the previous were different or we are finished
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if (last_seen_bit_count > 1) {
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// insert a loop
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state_sequent *rep_sequence = new state_sequent();
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rep_sequence->repeat = last_seen_bit_count;
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register_ttls->ttls = (1 << DATA_BIT) * last_seen_bit + (1 << CLK_BIT) + (1 << latch_bit);
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rep_sequence->push_back(register_state->copy_new());
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register_ttls->ttls = (1 << DATA_BIT) * last_seen_bit + (1 << latch_bit);
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rep_sequence->push_back(register_state->copy_new());
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the_sequence.insert(the_state, rep_sequence);
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} else {
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// no loop necessary, insert two states
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register_ttls->ttls = (1 << DATA_BIT) * last_seen_bit + (1 << CLK_BIT) + (1 << latch_bit);
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the_sequence.insert(the_state, register_state->copy_new());
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register_ttls->ttls = (1 << DATA_BIT) * last_seen_bit + (1 << latch_bit);
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the_sequence.insert(the_state, register_state->copy_new());
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}
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// reset counter and bits if we are not finished
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if (i < (DAC_DATA_BITS + DAC_CONTROL_BITS)) {
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last_seen_bit = dac_word[i];
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last_seen_bit_count = 1;
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}
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} // finished writing
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else
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last_seen_bit_count += 1; // same bit value, so continue
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} // end of bit loop
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register_ttls->ttls = 0;
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the_sequence.insert(the_state, register_state->copy_new());
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// shorten the remaining state
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// and add LE high to this state
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ttlout *ttls = new ttlout();
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// 2 clocks per bit + 1 for sync
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this_state->length -= TIMING * 2 * (DAC_DATA_BITS + DAC_CONTROL_BITS) + 1;
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ttls->ttls = 1 << latch_bit;
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this_state->push_front(ttls);
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// cleanup
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delete register_state;
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delete dac_analog_out;
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} // state was long enough to work on
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} else {
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ttlout *le_ttls = new ttlout();
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// le_ttls->ttls = 1 << latch_bit;
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this_state->push_back(le_ttls);
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}
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// end of state modifications
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} // I was a state
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}
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